High-Speed Interface Production Ready

PCIe Gen 6
IP Core

64 GT/s PAM4 interface with FLIT mode encoding — the industry's most advanced PCIe generation for AI training clusters, CXL memory expansion, and next-gen data center platforms.

FPGA Validated PCIe 6.0 Compliant ASIC Ready ARM/RISC-V SoC

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Key Specifications

64 GT/s

Data Rate / Lane

x1–x16

Lane Config

256 GB/s

Peak BW (x16)

AXI4

System Interface

Platform Support

XilinxAlteraMicrochipLatticeCustom ASIC

Backward Compatible

Gen 1Gen 2Gen 3Gen 4Gen 5

Overview

Next Frontier in High-Speed Connectivity

64 GT/s

Per Lane

256 GB/s

x16 Bandwidth

PAM4

Signaling

FLIT

Mode Encoding

PCIe Gen 6 doubles the throughput of Gen 5 by adopting PAM4 modulation and FLIT-mode encoding — delivering 64 GT/s per lane and 256 GB/s peak bidirectional bandwidth in a ×16 configuration.

Xtremesilica's Gen 6 IP core implements the complete PCIe 6.0 Base Specification including the new FLIT-based transaction layer, L0p low-power link state, and 1b/1b FEC. The core is delivered as synthesizable SystemVerilog RTL compatible with all major FPGA families and any ASIC process node from 180 nm down to 3 nm.

Full backward compatibility ensures seamless operation with existing Gen 1 through Gen 5 devices, protecting your platform investments while enabling next-generation performance.

256 GB/s Bidirectional

PCIe 6.0 x16 delivers the highest bandwidth in the PCIe family — ideal for AI training GPUs and CXL memory pooling at scale.

FLIT Mode + 1b/1b FEC

Fixed 256-byte FLIT frames with lightweight FEC eliminate the traditional credit-based flow control overhead, reducing latency significantly.

Features

Built for the Next Generation

64 GT/s PAM4 Signaling

PAM4 modulation doubles bandwidth per lane versus NRZ, delivering 64 GT/s while maintaining full backward compatibility with Gen 1–5 devices.

FLIT Mode Encoding

Fixed 256-byte FLIT-based transaction layer with optional 1b/1b FEC. Eliminates variable-latency TLP framing, enabling ultra-low, deterministic latency.

Scalable x1–x16 Lane Width

Compile-time lane-width parameter supports x1, x2, x4, x8, x16 configurations with matching AXI4-Stream interface widths of 64–2048 bits.

L0p Low-Power State

New PCIe 6.0 L0p partial lane-width power state reduces dynamic power by up to 50% when full bandwidth is not required, ideal for power-sensitive deployments.

CXL 3.0 Ready

PCIe Gen 6 is the physical layer for CXL 3.0. Our IP includes CXL mode negotiation support for memory-coherent accelerator and memory-expansion use cases.

Advanced Error Reporting

Full PCIe AER support, MSI/MSI-X interrupts, hardware-assisted error recovery, and real-time performance counters with optional ILA/SignalTap hooks.

Specifications

Complete Technical Specifications

Physical Layer

Spec VersionPCIe Base Spec 6.0

Data Rate64.0 GT/s per lane

ModulationPAM4

EncodingFLIT mode (256-byte)

FEC1b/1b optional

Lane Configsx1, x2, x4, x8, x16

Peak BW (x16)256 GB/s bidirectional

Backward CompatGen 1 / 2 / 3 / 4 / 5

Transaction Layer

FLIT Frame Size256 bytes fixed

Max Payload256–4096 bytes

TLP TypesMRd/MWr/Cpl/CplD/IO/Cfg/Msg

Tagged Requests512 tags (10-bit)

Address Width32-bit and 64-bit

OrderingRelaxed / ID-based

System Interface

Primary InterfaceAXI4-MM (64–2048-bit)

ManagementAXI4-Lite (32-bit)

DMAScatter-gather (optional)

Interrupt ModeLegacy / MSI / MSI-X

CXL ModeCXL 3.0 negotiation

Power Management

Link StatesL0, L0p, L0s, L1, L1.1, L1.2

L0p ModePartial-width (new Gen 6)

ASPML0p, L0s, L1 autonomous

Device StatesD0, D3hot, D3cold

RTL LanguageSystemVerilog IEEE 1800

ASIC Nodes180 nm → 3 nm

Platforms

FPGA & ASIC Platform Support

Xilinx (AMD)

Vivado / Vitis

Versal Premium ACAP with GTM transceiversVivado IP Integrator BD componentXDC timing constraints includedZynq PS-PL AXI bridge integration

Altera (Intel)

Quartus / Platform Designer

Agilex 9 with SERDES at 64 GT/sPlatform Designer componentSDC timing constraintsHPS AXI bridge example design

Microchip

Libero SoC

PolarFire SoC SmartDesign componentPDC constraint filesMi-V RISC-V subsystem integrationRadiation-tolerant variant available

Custom ASIC

Any Foundry / Any Node

Synthesizable SystemVerilog RTLSynopsys / Cadence synthesis scriptsSDC timing constraintsOptional GDS layout delivery

Applications

Where PCIe Gen 6 Excels

🤖

AI Training Clusters

Connect GPUs and NPUs at 256 GB/s for large-model training with minimal host-accelerator bottleneck.

🧠

CXL Memory Pooling

PCIe 6.0 underpins CXL 3.0 for cache-coherent, disaggregated memory across multi-host systems.

💾

NVMe Gen 6 SSDs

Storage controllers leveraging full Gen 6 bandwidth for all-flash arrays and latency-critical applications.

🌐

SmartNIC / DPU

Data-plane offload NICs requiring maximum PCIe throughput for 400G and 800G Ethernet line rate.

🔬

HPC Interconnect

Scientific computing clusters connecting FPGAs, custom accelerators, and CPUs at maximum bandwidth.

🏎️

Automotive ADAS

High-bandwidth sensor-fusion SoCs for advanced driver-assistance and autonomous driving platforms.

☁️

Hyperscale Cloud

Custom cloud ASICs replacing merchant silicon with in-house SoCs optimized for Gen 6 performance.

📡

5G/6G Baseband

Fronthaul and backhaul processing units requiring ultra-high-bandwidth PCIe bus connectivity.

Deliverables

Everything You Need to Integrate

FPGA Implementation

Xilinx Vivado project + IP Integrator BDAltera Quartus + Platform Designer componentMicrochip Libero SoC SmartDesignPlatform-specific XDC/SDC/PDC constraints

Custom ASIC Implementation

Synthesizable RTL (SystemVerilog)SDC timing constraintsSynopsys / Cadence synthesis scriptsARM / RISC-V SoC integration reference

Verification Suite

UVM testbench with 100% functional coveragePCIe 6.0 compliance test suiteDirected + constrained-random regressionInteroperability test report

Documentation

Architecture & micro-architecture specRegister map & programming guideFPGA integration quick-start guideLinux / RTOS driver source & guide

PCIe Gen 6IP Core