Memory Controller Production Ready FPGA Validated ASIC Ready

DDR5
Controller IP Core

Next-generation DDR5 SDRAM controller up to 6400 MT/s with on-die ECC, dual sub-channel architecture, and 51.2 GB/s peak bandwidth. Tailored for any FPGA or custom ASIC on your preferred fab and technology node.

FPGA Validated

JEDEC DDR5 Compliant

Custom ASIC Ready

ARM / RISC-V SoC

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Key SpecificationsRev 1.5

6400MT/s Max Rate

51.2GB/s Bandwidth

1.6×vs DDR4

ECCOn-Die ECC

Platform Support

XilinxAlteraMicrochipCustom ASIC

Standards

JEDEC DDR5 ✓JESD79-5Dual sub-ch

Product Overview

51.2 GB/s Peak Bandwidth.
1.6× Faster than DDR4.

The Xtremesilica DDR5 Controller delivers up to 6400 MT/s data rates with 51.2 GB/s peak bandwidth per 64-bit channel — a 1.6× improvement over DDR4-3200 — making it the ideal memory subsystem for AI training, HPC, and datacenter applications.

The dual sub-channel (2×32-bit) architecture enables independent access to each 32-bit sub-channel, doubling effective command bandwidth. Built-in on-die ECC, CRC error detection, and command/address parity ensure mission-critical reliability. Operating at 1.1V (vs 1.2V for DDR4), the controller delivers approximately 20% lower power consumption. Whether targeting Xilinx Versal, Intel Agilex, or a custom ASIC tape-out on your preferred foundry, the same verified RTL ships with full PHY interface support and a comprehensive UVM verification suite.

6400 MT/sMax data rate

51.2 GB/sPeak bandwidth

20%Lower power

Any FabAny node, your choice

Capabilities

Feature Highlights

Every layer engineered for maximum bandwidth, reliability, and seamless SoC integration.

Enhanced Bandwidth — 51.2 GB/s

Up to 6400 MT/s data rate delivering 51.2 GB/s per 64-bit channel, providing 1.6× bandwidth improvement over DDR4-3200 for memory-hungry workloads.

6400 MT/s51.2 GB/s1.6× DDR4

Dual Sub-Channel Architecture

Two independent 32-bit sub-channels per 64-bit DDR5 module enable improved bank utilisation, higher command efficiency, and true independent sub-channel access.

2×32-bit channelsIndependent accessBank groups

On-Die ECC & Reliability

Built-in on-die error correction within the DRAM device, command/address parity, and CRC error detection for mission-critical reliability without bandwidth overhead.

On-die ECCCRC detectCA parity

Power Efficiency — 1.1V Operation

Reduced operating voltage (1.1V vs 1.2V for DDR4) and advanced power management features deliver approximately 20% lower total power consumption.

1.1V VDD~20% less powerPower gating

Flexible Refresh Management

Same Bank Refresh (SBR), dual sub-channel independent refresh, and per-bank refresh group scheduling for improved availability and reduced refresh overhead.

SBRPer-bank refreshIndependent

Advanced Command Scheduling

Intelligent bank group management, rank interleaving for up to 4 ranks per channel, and adaptive timing optimisation to minimise latency and maximise throughput.

4-rank supportRank interleaveAdaptive timing

Technical Data

Full Specifications

Complete parameter set for system architecture and integration planning.

Memory Standard

Standard

JEDEC DDR5 SDRAM (JESD79-5)

Data Rate

4800–6400 MT/s

Roadmap

Up to 8400 MT/s

Operating Voltage

1.1V VDD / VDDQ

vs DDR4

1.6× bandwidth, ~20% lower power

Channel Architecture

Peak Bandwidth

51.2 GB/s per 64-bit ch

Sub-Channels

Dual 32-bit sub-channels

DRAM Device Width

×4, ×8, ×16

Rank Support

Up to 4 ranks per channel

Burst Length

BL16, BL32 (OTF)

Reliability & ECC

On-Die ECC

DRAM on-die ECC supported

CRC

Write data CRC detection

CA Parity

Command/address parity

Refresh

SBR, per-bank, independent sub-ch

Temperature

DRAM temperature monitoring

System Interface

Host Interface

AXI4 (64–512-bit data)

PHY Interface

Standard DDR5 PHY IF

RTL Language

SystemVerilog (IEEE 1800)

FPGA Support

Xilinx, Altera, Microchip

ASIC Technology

Any fab — 180nm → 3nm

Supported Platforms

FPGA & Custom ASIC Targets

Every platform ships with pre-tested constraints, example designs, and integration scripts.

Xilinx (AMD)

Vivado / Vitis

Versal ACAPVersal HBMZynq UltraScale+

Versal integrated DDR5 controller example
Vivado IP Integrator block design packaged
LPDDR5 / DDR5 PHY calibration scripts
XDC timing constraints included

Altera (Intel)

Quartus Prime Pro

Agilex F-SeriesAgilex I-SeriesStratix 10

Platform Designer DDR5 subsystem component
HPS DDR5 bridge example design
Memory calibration and margining scripts
SDC timing constraints included

Microchip

Libero SoC

PolarFire SoCPolarFire

SmartDesign memory controller component
Mi-V RISC-V AXI4 memory subsystem example
Low-power DDR5 configuration profile
PHY calibration TCL automation

Custom ASIC

Any Process Node

3nm / 5nm7nm / 12nm28nm / 180nm

Synthesisable RTL for any foundry
TSMC, Samsung, GlobalFoundries support
Full physical implementation service optional
GDS delivery + signoff reports

Use Cases

Target Applications

DDR5 is the memory backbone of modern AI, HPC, and datacenter platforms.

AI / ML Training Servers

High-bandwidth memory subsystem for AI training servers requiring rapid access to large model parameters and training datasets.

AI trainingModel paramsHigh bandwidth

Datacenter Servers

Main memory for enterprise cloud servers handling virtualised workloads, database operations, and multi-tenant applications at scale.

Cloud serverVirtualisationDatabase

High-Performance Computing

Memory subsystem for HPC supercomputer nodes processing scientific simulations, climate models, and large-scale numerical analysis.

SupercomputerScientificSimulation

Gaming PCs & Workstations

High-performance gaming systems and professional workstations demanding fast memory access for 4K/8K rendering and real-time graphics.

4K / 8K gamingCAD / 3DVideo editing

Network Infrastructure

Memory subsystem for routers, switches, and DPUs processing high-speed network traffic, routing tables, and packet forwarding lookups.

Router / switchDPUPacket processing

Embedded SoC / FPGA Systems

DDR5 memory subsystem for advanced SoC and FPGA-based systems requiring high bandwidth with low-power operation at the edge.

SoC integrationEdge AILow power

What You Receive

Deliverables Package

Everything needed to move from licence to tape-out in the shortest possible time.

FPGA Implementation

Xilinx Vivado project + IP Integrator BD
Altera Quartus Platform Designer component
Microchip Libero SmartDesign component
Platform-specific XDC / SDC constraints
DDR5 memory subsystem reference design

Custom ASIC Implementation

Synthesisable RTL (SystemVerilog)
SDC timing constraints for foundry signoff
Synopsys / Cadence synthesis scripts
GDS layout (optional backend service)
ARM / RISC-V SoC integration reference

Verification Suite

UVM testbench — 100% functional coverage
JEDEC DDR5 protocol compliance tests
Directed + constrained-random regression
ECC / CRC stress test report

Documentation

Architecture & micro-architecture spec
Register map & programming guide
FPGA integration quick-start guide
Linux / RTOS driver source & guide

DDR5Controller IP Core

51.2 GB/s Peak Bandwidth.1.6× Faster than DDR4.