UART VIP
Specification:
- Configurable Baud Rate Generator
- Auto Baud Rate Generation
- Error Detection
- Directed compliance tests
- System Verilog functional coverage model
- Configurable data-width with 5, 6, 7, 8 and 9-bits
- Supports 1 and 2 stop bits, parity (even, odd)
- False start bit detection
- Supports receiver FIFO with configurable depth
- SV/UVM
Deliverables in Verification Environment & Test Suite:
- Basic and Directed USB Protocol Tests
- Performance Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Regression Tests
- Documentation Guide