PCIE Gen5 VIP

Specification:

  • Compatible with PCIE Gen5 Base Spec V1.0 & PIPE Spec 6.0
  • SupportsTS1/TS2 Order Set changes for Gen5
  • Supports Polarity Inversion and lane reversal

PCIe Gen5 BFM/Agents for:

  • PHY Layer
  • Data Link Layer
  • Supports for Equalisation Bypass capability
  • Flow control credits management
  • Configurable functions up to 32 Physical functions and up to 256 Virtual functions, Functional Level Resets
  • Configurable link width x1, x2, x4, x8, x16
  • Supports address spaces for Memory, Configuration, IO
  • Configurable for PCIE Gen5 VIP as RC, EP And Switch
  • Supports SRIOV
  • Configurable PIPE width 8,16,32,64 for SERDES 10,20,40,80

Deliverables in Verification Environment & Test Suite:

  • Directed Protocol Test cases
  • Random Test cases
  • Regression Tests
  • Connectivity Tests
  • Error Scenario Tests
  • Assertions & Cover Point Tests
  • Compliance Tests
  • System Verilog class-based API
  • Examples for Integration
  • Documentation