AXI 4.0 VIP

Specification:

  • Configurable data bus widths from 32bit to 512bit wide
  • Configurable address bus width
  • Transaction level protocol checking (burst type, length, size, lock type, cache type)
  • Full AXI4 /AXI4-Lite Protocol checker
  • Supports UVM RAL Model
  • Supports Error Injection
  • AXI4 Master Slave agent, Bus Monitor and score boarding

Deliverables in Verification Environment & Test Suite:

  • Directed Protocol Test cases
  • Random Tests cases
  • Error Scenario Cases
  • Assertions & Cover Point Tests
  • Integration Examples
  • Documentation Guide