USB 3.2/4.0

Integrates MAC IP to a broad range of PHY and SerDes IP

Overview

The DesignWare USB 3.2 IP is targeted for integration into SoCs for mass storage devices, video, automotive applications, graphics adaptors, requiring increased bandwidth between PCs and portable electronic devices. Optimised for low power, the DesignWare USB 3.2 Controller and PHY IP allow designers to maximize power efficiency for extended battery life. The DesignWare USB 3.2 IP enables the fastest SuperSpeed USB data transfer speeds, at 20Gbps, while lowering overall power consumption.

The IP supports USB Type-C connectivity with the DesignWare USB-C 3.2 IP, which simplifies users’ USB connection with reversible plug orientation and cable direction, and bi-directional power. The DesignWare USB-C 3.2 IP also supports features required for the USB Audio Device Class 3.0 specification to enable USB audio over Type-C connections

diagram

Features

  • Fully compliant with USB 3.2 specification version 1.1, xHCI Specification Revision 1.2, and Pipe Interface 6.1.1 with Message Bus Interface for USB3.2 Architecture with backward compatibility to USB3.1, USB3.0 and USB2.0 (including USB2.0, USB 3.0. OTG).
  • Supports USB Type-C.
  • Supports up to 128 devices including hub and device on any tier level.
  • Supports 15 IN and 15 OUT and 1 control endpoint for each device.
  • Supports all transfer types; Control, Bulk, Bulk Stream, Interrupt with flow control and retry mechanism.
  • Support for pipelined isochronous and Smart Isochronous transfer.
  • Supports configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints.
  • Supports out of band active stream list exchange, HIMD and Stream Proposal rejection feature.
  • Supports bursting in all transfer modes (Up to Max Burst size).
  • SuperSpeedPlus supports Precision Time Measurement (PTM) (LDM protocol).
  • Enhanced traffic and flow control management in link layer.
    • Supports both Type 1 And Type 2 Traffic Classes.
    • Different Header packet framing for Deferred and Non-Deferred DPH.
  • Supports all compliance patterns – CP0 to CP8 over Gen 1 Rate and CP9 to CP16 over Gen 2 Rate for Compliance Mode LTSSM state.
  • Support for all power management states (U1, U2, U3) with U1 Inactivity, U2 Inactivity timers.
  • Support for generation of all link commands defined in the USB3.2 Specification.
  • Dual lane support (Gen2x2 and Gen1x2) with Skew and De-Skew capabilities with SSC/PPM support.
  • Configurable PIPE Interface width – 8b,16b or 32b.
  • User controlled device attach/ detach function.
  • Supports UAS (USB Attached SCSI) and BOT (Bulk-Out Transfer).
  • Configurability to enable required data rate (8b/10b or 128b/132b) & Speed negotiation (x1 or x2).
  • Comprehensive Compliance Test Suite for Physical, Link and Protocol Layer, xHCI Verification.
  • Call backs support in all Layers to provide user-controlled error injection.
  • Automated masking of all types of error injections.
  • Complete on-the-fly Static and Dynamic Assertion Protocol Checks.
  • Built-in Functional coverage analysis.

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