UCLe

Integrates MAC IP to a broad range of PHY and SerDes IP

Overview

Universal Chiplet Interconnect Express (UCIe) is structured around a three-layer model, which ensures efficient communication and integration of chiplets within a package. Flit aware Die-to-Die interface (FDI) between Protocol layer and Die to Die adapter, Raw Die-to-Die Interface (RDI) between Die-to-Die adapter and Physical layer, and Physical link interface between two dies – for single and multi-module chiplet setups. These layers are designed to provide a comprehensive and standardized approach to inter-chiplet communication, addressing different aspects of the interconnect such as physical connections, data transfer protocols, and logical operations.

diagram

Features

  • Support PCI Express (PCIe 6.0) and Compute Express Link (CXL 2.0, CXL 3.0) protocols.
  • Supports CXL 2.0 68B Flit Mode, CXL 256B Flit Mode, PCIe 6.0 Flit Mode and Raw Mode for all protocols.
  • Supports streaming protocol for Raw format.
  • Support decision table for flit format and protocol in d2d adapter layer.
  • Supports multiple stacks/multiple protocols.
  • Supports AXI 3 & 4 Protocols using Raw format.
  • Supports standard (2D) and Advanced package (2.5D).
  • Supports link speeds up to 32GT/s.
  • Supports single-module, two-module and four-module configuration.
  • Support for power management link states.
  • Supports up to 16 Gbps per pin including 4/8/12Gbps.
  • Available with 8/16/32 and 64 lanes.
  • Support directed and randomised flit generation.
  • Support for ARB/MUX, CRC retry, link state management, parameter negotiation, link training, scrambling/descrambling, sideband training transfers, lane repair, lane reversal.
  • Support mainband/sideband interfaces and FDI/RDI interfaces.
  • Supports Flow control and Retry mechanism.
  • Supports runtime Link Testing through Parity, Scrambling/De-scrambling.
  • Supports all kinds of side-band messages.
  • Supports LTSM, RDI state machine and FDI state machine.
  • Supports single and multiple CXL stacks with internal ARB/MUX layer.
  • Available with in-built UCIe Retimers.

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