PCIe Gen 4/5/6

Integrates MAC IP to a broad range of PHY and SerDes IP

Overview

PCI Express (PCIe) 6.x complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, verification and Integrity and Data Encryption (IDE) security module IP.Leveraging decades of engineering expertise to develop robust IP solutions for PCIe through all the generations of the specification, PCI Express (PCIe) 6.x is optimised to support the latest PCIe 6.x specification including PAM-4 signaling, FLIT mode, L0p power state, and more to allow a seamless migration to PCIe 6.x designs.

diagram

Features

  • Compliant with PCI Express Specifications 6.1 (64GT/s), 5.0 (32GT/s), 4.0 (16GT/s), 3.1 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
  • Support for 64.0 GT/s Data Rate per lane with backwards compatibility.
  • Support for new PAM4 Signalling and Grey Coding.
  • Support for both Flit Mode & Non-Flit Model.
  • Support for TS0 ordered set (Equalisation at 64bit).
  • Support for Precoding at 32GT/s and 64GT/s.
  • Support for New Power Management state L0p.
  • Configurable Link Width: x1, x2, x4, x8, x16 (x12 and x32 in Non-flit Mode).
  • Supports Low Power management LTSSM states – L1, L2, L1 sub states, PCI- PM, ASPM.
  • Compliant with latest PIPE Specification 6.2.
  • Supports SerDes PIPE Architecture as well as Original PIPE Architecture.
  • Supports Low Pin Count Interface as well as Legacy PIPE Interface.
  • Configurable PIPE width support:
    • Original PIPE Arch. – 8, 16, 32, 64.
    • SerDes PIPE Arch. – 10, 20, 40, 80.
  • Support for Shared Flow Control Mechanism.
  • Supports 14-bit Tag as requester as well as completer.
  • Supports Non-Posted Deferrable Memory Writes.
  • Advanced Error Reporting (AER) with optional Malformed TLP checks, ECRC and TLP Poisoning support.
  • Support for optional extended capabilities such as:
    • Flit Error Injection Extended Capability.
    • VF Resizable Bar Extended Capability.
    • Data Object Exchange Extended Capability.
  • Supports simplified replay timer and SR-IOV.
  • Support for ATS with latest ATS Specification v1.1.
  • Supports LTR & FLR (Function Level Reset).
  • Support for SSC and Jitter in clock.
  • Support for Common RefClk and Separate RefClk.
  • Compliance testing in TL, DLL & PL including power management test-suites.
  • Support for Flit Logging Ext ended Capability.
  • On the fly protocol checking using protocol check functions, static and dynamic assertion.
  • Built in Coverage analysis.
  • Provides a comprehensive user API (call backs).
  • Verification IP configurable as PCI express Root Complex, Device Endpoint or PCIe Switch.
  • Support for Block Level Verification.
  • Graphical analyser for all three Layers to show PCIe transactions for easy debugging.

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