GDDR4/5 Controller

Overview

GDDR4 DFI Verification IP provides an smart way to verify the GDDR4 DFI component of a SOC or a ASIC. The SmartDV’s GDDR4 DFI Verification IP is fully compliant with standard DFI Specification and provides the following features. GDDR4 DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env. GDDR4 DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

GDDR5 Memory Model provides an smart way to verify the GDDR5 component of a SOC or a ASIC. The SmartDV’s GDDR5 memory model is fully compliant with standard GDDR5 Specification and provides the following features. Better than Denali Memory Models. GDDR5 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env. GDDR5 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features

GDDR4

  • Compliant with DFI version 4.0 or 5.0 Specifications.
  • Supports GDDR4 devices compliant with JEDEC GDDR4 SGRAM Standard GDDR4Spec_rev_04.
  • Supports all Interface Groups.
  • Supports Write Transactions with Data mask.
  • Supports DRAM Clock disabling feature.
  • Supports Data bit enable/disable feature.
  • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
  • Supports frequency change protocol.
  • Supports Low power control features.
  • Supports Error signaling.
  • Supports DFI Read/Write Chip Select.
  • Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat, tphy_wrdata, trd_dataen and tphy_rdlat delays.
  • Constantly monitors DFI behavior during simulation.
  • Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.
  • Bus-accurate timing for min, max and typical values.
  • Notifies the test bench of significant events such as transactions, warnings.
  • Built in functional coverage analysis.
  • Supports callbacks, so that user can access the data observed by monitor.

GDDR5

  • Supports GDDR5 memory devices from all leading vendors.
  • Supports 100% of GDDR5 protocol standard JESD212C.
  • Supports all the GDDR5 commands as per the specs.
  • Quickly validates the implementation of the GDDR5 standard JESD212 and JESD212C.
  • Supports for programmable clock frequency of operation.
  • Supports for all types of timing and protocol violation detection.
  • Supports up to 8GB device density.
  • Supports the following device modes:
    • X16
    • X32
  • Supports All Mode register programming.
  • Checks for the following:
    • Check-points include power on, initialisation and power off rules.
    • State based rules, Active Command rules.
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports for Single ended interface for command, address and data.
  • Supports Double Data Rate (DDR) data (WCK).
  • Supports Single Data Rate (SDR) command (CK).
  • Supports Double Data Rate (DDR) addressing (CK).
  • Support for Programmable Burst length 8.
  • Support for Programmable read latency and write latency.
  • Supports for Write data mask function via address bus.
  • Support for Data bus inversion (DBI) & address bus inversion (ABI).
  • Supports for Input/output PLL/DLL.
  • Support for Address training.
  • Supports for cyclic redundancy check (CRC-8).
  • Support for Programmable CRC read latency, write latency.
  • Support for Low Power modes.
  • Support for Auto & self-refresh modes.
  • Supports the Auto Precharge option for each burst access.
  • Supports for On-die termination (ODT) for all high-speed inputs.
  • Supports input clock stop and frequency change.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Protocol checker fully compliant with GDDR5 Specification JESD212 and JESD212C.
  • Constantly monitors GDDR5 behaviour during simulation.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

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