CXL

Integrates MAC IP to a broad range of PHY and SerDes IP

Overview

Compute Express Link (CXL) 2.0 is the next iteration of the CXL standard, building upon the foundation established by CXL 1.0 and 1.1. CXL 2.0 introduces several new features and enhancements aimed at further improving performance, scalability, and resource efficiency in modern computing environments. This makes it particularly suitable for high-performance computing (HPC), artificial intelligence (AI), machine learning (ML), and cloud data centers.

diagram

Features

  • Support CXL specifications revision 1.0, 1.1 and 2.0.
  • Verification IP configurable as CXL Host and Device when operating in Flex Bus mode and as PCI Express Root Complex and Device Endpoint when operating in PCIe mode.
  • Support for all three CXL protocols i.e., CXL.io, CXL.cache, CXL.mem, and device types to meet specific application requirements with user-configurable memory size for both CXL Host and Device.
  • Support for CPI(CXL-Cache/Mem Protocol Interface).
  • Supports the signaling rate of 32 GT/s, degraded rate of 16 GT/s or 8 GT/s in CXL mode.
  • Support for Alternate Protocol Negotiation for CXL Mode.
  • Support Pipe Specification 5.1 with both Low Pin Count and Serdes Architecture.
  • Support all CXL.Cache/CXL.mem request and response messages.
  • Support for CXL ALMP transmission and reception to control virtual link state machine and power state transition requests.
  • Support for CXL ACK forcing and Link Layer Credit exchange mechanism.
  • Support Arbitration among the CXL.IO,CXL.cache and CXL.mem packets with Interleaving of traffic between different CXL protocols.
  • Supports configuration of PCIe vs CXL protocol mode.
  • Support for randomization and user controllability in flit packing.
  • Support for CXL Link Layer Retry Mechanism.
  • Support for Configurable timeout for all three layers.
  • Support for different CXL/PCIe Resets.
  • Support for power management including the low power L1 with sub-state and L2.
  • Provides a comprehensive user API (callbacks).
  • Flit support for 256B standard, 256B Lopt, 68B, and all other flit types supported for each layer.
  • Support configuration Space Registers, Memory Mapped Registers.

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