High-Speed InterfaceProduction Ready

USB 4.0
IP Core

40 Gbps USB 4.0 with Thunderbolt 3 compatibility, DisplayPort alternate mode, and USB-C power delivery — the universal connectivity solution for modern FPGA and ASIC designs.

FPGA Validated USB4 Spec Compliant TB3 Compatible ASIC Ready

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Key Specifications

40 Gbps

Max Throughput

USB-C

Connector Type

100W

Power Delivery

DP 2.0

Alt Mode

Platform Support

XilinxAlteraMicrochipCustom ASIC

Backward Compatible

USB 3.2USB 2.0TB3

Overview

Universal Connectivity at 40 Gbps

40 Gbps

Total Bandwidth

100W

Power Delivery

TB3

Compatible

DP 2.0

Alternate Mode

USB 4.0 unifies the USB and Thunderbolt ecosystems into a single 40 Gbps interface over the USB-C connector. Xtremesilica's USB 4.0 IP core implements the complete USB4 specification including tunnel protocols for USB 3.2, PCIe, and DisplayPort over a single cable.

The IP core is delivered as synthesizable RTL for FPGA prototyping and ASIC tapeout, with comprehensive USB-IF compliance test support and a full UVM verification environment.

Features

Complete USB 4.0 Feature Set

40 Gbps Symmetric

Full 40 Gbps in both directions simultaneously, with intelligent bandwidth allocation between USB, PCIe, and DisplayPort tunnel streams.

Thunderbolt 3 Compatible

Full Thunderbolt 3 host and device compatibility, enabling access to the broad TB3 peripheral ecosystem from USB 4.0 hosts.

DisplayPort Alternate Mode

DisplayPort 2.0 tunneling for 8K display output over USB-C. Simultaneous data transfer and video output with optimized bandwidth sharing.

USB Power Delivery 3.1

Up to 100W (20V @ 5A) power delivery with PPS (Programmable Power Supply) for flexible device charging and bus-powered peripherals.

Multi-Protocol Tunneling

Simultaneous USB 3.2 Gen 2×2, PCIe Gen 3, and DisplayPort 2.0 tunnel streams over a single USB4 link with QoS scheduling.

USB-C CC/PD Controller

Integrated USB-C CC logic and PD 3.1 controller for cable orientation detection, role negotiation, and power delivery negotiation.

Specifications

Complete Technical Specifications

Physical Layer

Spec VersionUSB4 Version 1.0

Max Data Rate40 Gbps (Gen 3×2)

ConnectorUSB Type-C

Cable LengthUp to 2 m (passive)

Lanes2 × Gen3 (20 Gbps each)

Encoding128b/132b

Protocol Tunneling

USB TunnelUSB 3.2 Gen 2×2 (20G)

PCIe TunnelPCIe Gen 3 ×4

DP TunnelDisplayPort 2.0 (UHBR)

TB3 CompatFull host & device

USB 2.0Backward compatible

Power Delivery

PD VersionUSB PD 3.1

Max Power100 W (20V × 5A)

PPSProgrammable Power Supply

CC LogicIntegrated USB-C CC

VCONNActive cable support

Implementation

RTL LanguageSystemVerilog

Host InterfaceAXI4-MM / AXI4-Stream

FPGA SupportXilinx, Altera, Microchip

ASIC Nodes5 nm → 28 nm

VerificationUVM, USB-IF compliance

Platforms

FPGA & ASIC Platform Support

Xilinx (AMD)

Vivado / Vitis

Versal AI Core Series integrationGTY transceiver PHY supportVivado IP Integrator block designXDC timing constraints

Altera (Intel)

Quartus / Platform Designer

Agilex 7 & Stratix 10 supportPlatform Designer componentTransceiver recalibration scriptsSDC timing constraints

Microchip

Libero SoC

PolarFire SoC SmartDesign componentLow-power SERDES configurationPDC constraint filesMi-V RISC-V integration example

Custom ASIC

Any Foundry / Any Node

Synthesizable SystemVerilog RTLPHY interface abstraction layerTSMC / Samsung / GF node supportUSB-IF certification support

Applications

Where USB 4.0 Excels

💻

Laptops & Ultrabooks

Single-cable docking solutions delivering power, data, and 8K display over one USB-C connector.

🎮

Gaming Peripherals

External GPU enclosures and high-bandwidth storage arrays connected via USB4/Thunderbolt 3.

📷

Professional Cameras

RAW video capture and real-time streaming at 8K resolution with simultaneous power delivery.

🔬

Test & Measurement

High-speed data acquisition systems requiring maximum USB throughput and low-latency control.

🏭

Industrial Automation

Machine vision cameras and industrial controllers requiring reliable, high-bandwidth USB connectivity.

🩺

Medical Imaging

Ultrasound, MRI, and endoscopy systems transferring large image datasets with minimal latency.

🚗

Automotive Infotainment

In-vehicle infotainment hubs with USB4 for smartphone mirroring and high-definition display output.

📱

Mobile SoCs

Next-generation mobile processors with integrated USB4 for laptop-class performance on smartphones.

Deliverables

Everything You Need to Integrate

FPGA Implementation

Xilinx Vivado project + IP Integrator BDAltera Quartus + Platform DesignerMicrochip Libero SoC SmartDesignPlatform-specific constraint files

Custom ASIC Implementation

Synthesizable RTL (SystemVerilog)PHY wrapper for target foundrySynthesis scripts (Synopsys/Cadence)ARM/RISC-V SoC integration guide

Verification Suite

UVM testbench, 100% functional coverageUSB-IF compliance test supportProtocol tunnel stress testsInteroperability test report

Documentation

Architecture & micro-architecture specRegister map & programming guideIntegration quick-start guideLinux driver source & porting guide

Ready to Integrate USB 4.0?

Production-ready IP with full USB-IF compliance and ASIC delivery in weeks.

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USB 4.0IP Core

Universal Connectivity at 40 Gbps

Complete USB 4.0 Feature Set

Complete Technical Specifications

FPGA & ASIC Platform Support

Where USB 4.0 Excels

Everything You Need to Integrate

USB 4.0
IP Core