High-Speed InterfaceProduction Ready

USB 3.2
IP Core

20 Gbps SuperSpeed+ USB 3.2 Gen 2×2 with dual-lane operation, Battery Charging 1.2, and full backward compatibility. The proven USB solution for storage, industrial, and consumer electronics.

FPGA Validated USB-IF Certified BC 1.2 Support ASIC Ready
Key Specifications
20 Gbps
Max Rate (Gen2×2)
Dual Lane
Configuration
128b/132b
Encoding
BC 1.2
Charging
Platform Support
XilinxAlteraMicrochipLatticeCustom ASIC
Backward Compatible
USB 3.1USB 3.0USB 2.0

SuperSpeed+ at 20 Gbps

20 Gbps
Peak Rate
2×10G
Dual Lane
128b/132b
Encoding
BC 1.2
Fast Charging

USB 3.2 Gen 2×2 achieves 20 Gbps by bonding two 10 Gbps lanes over a USB-C cable, using 128b/132b encoding for improved efficiency over the older 8b/10b used by USB 3.1. Xtremesilica's IP core delivers a complete host and device controller implementation with power management and Battery Charging 1.2 support.

The core is field-proven across Xilinx, Altera, Microchip, and Lattice FPGAs and fully synthesizable for custom ASIC at any technology node from 28 nm to 5 nm.

Ready to Integrate USB 3.2?
Production-proven IP core delivered in weeks for FPGA or ASIC.