Chiplet InterconnectProduction Ready

UCIe
IP Core

Universal Chiplet Interconnect Express — the open die-to-die interconnect standard enabling multi-vendor chiplet ecosystems, advanced 2.5D/3D packaging, and scalable disaggregated SoC designs.

UCIe 1.1 Compliant 2.5D / 3D Packaging Multi-Protocol ASIC Ready
Key Specifications
16 TB/s
Advanced Pkg BW
2 TB/s
Standard Pkg BW
Multi
Protocol Support
UCIe 1.1
Spec Version
Protocols Tunneled
PCIeCXLStreaming
Packaging
Advanced 2.5DStandard (BoS)3D

The Open Chiplet Interconnect Standard

16 TB/s
Advanced Pkg BW/mm
2 TB/s
Standard Pkg BW/mm
<2 ns
Die-to-Die Latency
PCIe/CXL
Protocol Tunnels

UCIe (Universal Chiplet Interconnect Express) is the open industry standard for die-to-die connectivity, enabling chiplets from different vendors to communicate with consistent signaling and protocol semantics. Supported by Intel, AMD, ARM, Samsung, TSMC, and 80+ industry members, UCIe is the foundation of the emerging chiplet economy.

Xtremesilica's UCIe IP core delivers the complete PHY, D2D adapter, and protocol tunnel layers for both Advanced (wafer-level, interposer) and Standard (organic substrate) package formats, with PCIe Gen 5/6 and CXL tunneling.

Ready to Build Chiplet Systems?
UCIe 1.1 IP core — the foundation of your chiplet ecosystem.