16550-compatible UART controller with programmable baud rate generator, configurable TX/RX FIFOs up to 64 bytes, hardware RTS/CTS flow control, IrDA SIR mode, and APB/AXI4-Lite register interface — the universal serial debug and communication peripheral for any SoC.
The UART Controller IP delivers a fully 16550A-compatible universal asynchronous receiver/transmitter with extended features for modern SoC designs. Configurable TX and RX FIFOs (8 to 64 bytes), a fractional baud-rate generator for precise baud rates from any system clock, and hardware RTS/CTS flow control make this IP a drop-in replacement for any legacy 16550 peripheral bus peripheral.
Extended features include IrDA SIR mode for infrared communication, RS-485 half-duplex with automatic direction control, and DMA request outputs for zero-CPU bulk transfers. The tiny footprint (~500 LUTs on Xilinx UltraScale+) makes it economical to instantiate multiple instances in a single SoC for multi-port serial communication.