Serial InterfaceProduction Ready

SPI
Master/Slave

Flexible SPI master and slave controller supporting Standard, Dual, and Quad SPI modes with up to 8 chip-selects, configurable word width (4–32 bits), 64-byte TX/RX FIFOs, DMA interface, and all four CPOL/CPHA clock modes — the definitive SPI peripheral for flash, ADC, DAC, and sensor interfaces.

Standard / Dual / Quad SPI 100 MHz SCK 8 Chip Selects DMA Ready

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Key Specifications

100 MHz

SCK (QSPI)

Chip Selects

4–32

Word Width

Dual

Master+Slave

SPI Modes

Mode 0Mode 1Mode 2Mode 3

Bus Width

StandardDualQuad

Overview

Versatile SPI for Flash, Sensors & High-Speed Peripherals

100 MHz

Max SCK

400 Mbps

QSPI Throughput

Chip Selects

<800

LUTs (FPGA)

The SPI Master/Slave Controller IP provides a complete, configurable SPI implementation supporting Standard (1-bit), Dual (2-bit), and Quad (4-bit) I/O modes for flash memory execute-in-place (XIP), high-speed ADC/DAC sampling, and peripheral communication. The IP operates simultaneously as master and slave through separate master and slave sub-blocks, allowing a single SoC instance to serve both roles.

All four CPOL/CPHA clock modes are supported, with per-slave configurability. Configurable TX/RX FIFOs (8–64 bytes), DMA request outputs, and interrupt coalescing minimise processor overhead for high-data-rate applications such as continuous ADC streaming and NOR flash firmware updates.

Features

Complete SPI Feature Set

Standard / Dual / Quad SPI

Full-featured SPI with 1-wire (standard), 2-wire (Dual SPI), and 4-wire (Quad SPI / QSPI) I/O modes selectable per transaction for flexible flash and peripheral use.

All CPOL/CPHA Modes

Mode 0 (0,0), Mode 1 (0,1), Mode 2 (1,0), and Mode 3 (1,1) per slave select, enabling connection to any SPI peripheral regardless of clock polarity/phase requirement.

8 Hardware Chip Selects

Up to 8 independent nCS outputs with configurable active-low/active-high polarity and programmable inter-CS and CS-to-CLK setup/hold times for each slave.

Configurable Word Width

Per-transaction data word width from 4 to 32 bits with MSB/LSB-first bit ordering, covering everything from 8-bit sensor reads to 16-bit ADC samples and 32-bit registers.

TX/RX FIFOs

Independent TX and RX FIFOs (8–64 entries, parameterised) with programmable watermark levels for interrupt and DMA burst threshold alignment.

DMA Interface

TX and RX DMA request outputs for CPU-free continuous data streaming — ideal for high-sample-rate ADC acquisition and NOR flash block programming/erase.

XIP / Memory-Mapped Mode

Execute-In-Place (XIP) mode maps QSPI NOR flash into the CPU address space for direct instruction fetch and data read without explicit transfer commands.

Slave Mode

Full SPI slave implementation with automatic nCS-triggered frame detection, configurable word width, and FIFO-backed operation for SoC-to-SoC communication.

Loopback & Test Mode

Internal loopback mode connects MOSI to MISO internally for self-test, enabling production test and firmware validation without external loopback hardware.

Specifications

Technical Specifications

SPI Interface

ModesStandard / Dual / Quad

Max SCK (std)50 MHz

Max SCK (QSPI)100 MHz

Clock ModesCPOL/CPHA 0/0,0/1,1/0,1/1

Word Width4–32 bits (runtime config)

Chip SelectsUp to 8 (nCS0–nCS7)

Bit OrderMSB / LSB first

FIFO & Control

TX FIFO8–64 entries (param.)

RX FIFO8–64 entries (param.)

DMATX/RX DREQ outputs

XIP ModeYes (AHB slave port)

Slave Mode

Slave SupportYes (concurrent M+S)

Max Slave SCKf_sys / 4

FIFO (slave)8–64 entries

Slave CS DetectHardware nCS edge

Implementation

FPGA (master)~800 LUTs (Xilinx US+)

ASIC Area~0.015 mm² @ 28 nm

Technology5 nm – 180 nm

Max Sys Clock400 MHz (ASIC)

Applications

Deployment Scenarios

💾

NOR Flash Boot

QSPI XIP boot from NOR flash for embedded processors — direct instruction fetch from flash-mapped address space with DDR QSPI support for maximum read throughput.

📈

High-Speed ADC/DAC

Continuous SPI DMA streaming from high-speed ADCs (up to 100 MSPS) and to DACs for signal-processing, test equipment, and software-defined radio applications.

🌡️

Sensor Hub

Multi-slave SPI bus aggregating accelerometers, gyroscopes, magnetometers, pressure sensors, and temperature ICs onto a single SPI controller with up to 8 CS lines.

🖥️

Display Interfaces

SPI-based TFT/OLED display controllers for small embedded displays requiring Mode 0/3 with configurable word widths for 8-bit command and 16/18-bit pixel data.

🔐

Secure Elements

SPI interface to TPM 2.0 chips, secure elements, and crypto-accelerator ICs for hardware-rooted security in IoT edge devices and automotive ECUs.

🔗

SoC-to-SoC Links

SPI slave mode for multi-chip system interconnects where one SoC acts as master and a second SoC as slave — compact, low-pin-count inter-chip communication.

Deliverables

What You Receive

RTL Source

Parameterised Verilog/VHDL RTL
Master and slave sub-blocks
Dual/Quad SPI I/O module
XIP AHB slave port

Verification Suite

UVM testbench with SPI VIP
All 4 CPOL/CPHA mode tests
Dual/Quad SPI protocol tests
XIP random-access test suite

Software Support

Linux spidev / SPI framework driver
FreeRTOS SPI HAL
Bare-metal HAL (C source)
QSPI NOR flash reference driver

Documentation

Integration guide & register map
QSPI NOR flash application note
XIP configuration guide
12-month technical support

Connect Any SPI Peripheral to Your SoC

From simple sensors to Quad-SPI NOR flash boot — get a quote for your target platform today.

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SPIMaster/Slave