UCLe

Integrates MAC IP to a broad range of PHY and SerDes IP

Overview

The UCLe (Ultra Compute Link Express) interface is a next-generation high-speed interconnect designed to facilitate seamless communication between various computing components such as CPUs, GPUs, memory modules, and hardware accelerators. UCLe aims to address the increasing demands for higher performance, lower latency, and enhanced efficiency in modern computing environments, particularly in data centers and applications involving AI/ML workloads.

diagram

Features

UCLe architecture is designed to provide a high-performance, coherent interconnect for communication between CPUs, memory, and accelerators.

UCLe Protocols

  • UCLe.io: Handles traditional I/O operations compatible with PCIe, managing configuration, interrupts, and DMA.
  • UCLe.cache: Enables low-latency, cache-coherent memory access, allowing devices to directly cache host memory for improved performance.
  • UCLe.memory: Facilitates direct access to memory across devices, enabling efficient data sharing and high-speed transfers.

UCLe Layers

  • Physical layer: Uses the PCIe physical and electrical interface for high data rates and advanced signalling.
  • Link layer: Manages data integrity, error correction, and flow control, ensuring reliable communication.
  • Physical layer: Manages specific communication tasks for I/O, cache coherence, and memory access, optimising data transfers and resource sharing.

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