Scatter-Gather DMA Engine

Integrates MAC IP to a broad range of PHY and SerDes IP

Overview

A Scatter-Gather Direct Memory Access (SG-DMA) engine is a specialised hardware component designed to efficiently transfer data between memory locations and peripherals without involving the CPU in the data transfer process. It allows data to be transferred to and from non-contiguous memory regions (scatter-gather), which enhances performance and flexibility in data-intensive applications such as networking, video streaming, and high-speed data acquisition.

diagram

Features

Components

  • DMA Controller: Central unit that manages and coordinates data transfers.
  • Address Generator: Generates addresses for reading from and writing to memory locations.
  • Scatter-Gather Table: Stores information about the memory regions involved in the data transfer.
  • Data Buffers: Temporary storage for data during transfer operations.
  • Transfer Engine: Handles the actual data transfer between memory and peripherals.
  • Interrupt Controller: Generates interrupts for various events such as transfer completion and errors.
  • Control Registers: Configurable registers for setting up and controlling DMA operations.
  • Error Detection and Correction Logic: Ensures data integrity by detecting and correcting errors during transfers.

Features

  • Efficient Data Transfer: Offloads data transfer tasks from the CPU.
  • Scatter-Gather Capability: Handles non-contiguous memory regions.
  • Low Latency: Minimises latency in data transfer.
  • High Throughput: Supports high-speed data transfer rates.
  • Flexible Configuration: Configurable for various data transfer patterns.
  • Error Handling: Ensures data integrity with error detection and correction.
  • Interrupt Support: Generates interrupts for efficient task management.

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