PCIe Gen 6

Enables high-speed, reliable data transfer between chips.

PRODUCT OVERVIEW

  • PCIe Gen 6.0 Silicon IP delivers ultra-high-speed interconnect at 64 GT/s per lane using PAM-4 signaling. With FLIT-mode support, integrated FEC, and PIPE 6.0 compliance, it ensures low-latency, high-bandwidth data transfers.
  • Designed for AI, cloud, HPC, storage, and networking, this IP core enables next-gen SoCs to connect CPUs, GPUs, FPGAs, and NVMe devices with exceptional throughput and efficiency in data-intensive applications.

PRODUCT ARCHITECTURE

PCIe Gen 6 Architecture

FEATURES

Discover the Difference

64 GT/s per Lane Bandwidth

Delivers up to 256 GB/s bidirectional throughput on x16 lanes using PAM-4 modulation.

Built-in FEC and LCRC

Ensures data integrity in noisy environments typical with PAM-4 signaling.

FLIT-Mode Transaction Layer

Fixed-length Flow Control Units with embedded FEC and CRC for improved reliability.

Low-Latency DMA Support

Integrated high-performance SG-DMA engines for efficient memory access.

PIPE 6.0-Compliant PHY Interface

Seamless PHY-Controller integration with standardized signaling.

Advanced Power Management

Supports L1/L2 states and sub-states for optimized power in mobile and server platforms.

Scalable Lane Configurations

Supports x1 to x16 with auto lane detection, polarity inversion, and dynamic equalization.

Virtualization-Ready Architecture

SR-IOV, ATS, PASID support for scalable, multi-tenant computing environments.

CONTACT US

GET IN TOUCH

Whether you’re looking to get in touch with us regarding a proposal, or just want to know more about us in general, feel free to contact us.

We’d be more than happy to assist you at the earliest.

info@xtremesilica.com

+91 79932 79934

Mon – Sat, 10:00hrs – 18:00hrs

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