100G TCP/IP Offload Engine

Integrates MAC IP to a broad range of PHY and SerDes IP

Overview

100G TCP Offloading Engine IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPUs are required. 100G TCP Offloading Engine IP built by pure hardwired logic can take the place of such extra CPU for TCP protocol management. This IP product includes reference design for FPGA. It helps you to reduce development time.

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Features

  • All pure hardware TCP/IP protocol stack for 100G bit Ethernet
  • Support IPv4 protocol
  • Support one port connection (Support Multi-session by implementing multiple cores).
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmitted packet size aligned to 512-bit, transmitted data bus size
  • Provide free evaluation bit file for FPGA Development Kits
  • Reference design is included in IP core product
  • Total receive data size aligned to 512-bit, received data bus size
  • Simple data interface by standard FIFO interface at 512-bit data bus, and Simple control interface by single-port RAM interface

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