Next-generation 32 GT/s controller with PAM4 signaling and x1–x16 lane configurations. Tailored for any FPGA platform or custom ASIC on your preferred fab and technology node.
The Xtremesilica PCIe Gen 5 IP core delivers 32 GT/s per lane using PAM4 signaling — doubling the bandwidth of PCIe Gen 4 while preserving full backward compatibility down to Gen 1.
Built on the same clean RTL architecture as our Gen 4 controller, it integrates directly into ARM Cortex and RISC-V processor subsystems via standard AXI4 interfaces — no glue logic required. Whether you're prototyping on Xilinx Versal or Stratix 10, or targeting a custom ASIC tape-out on your preferred fab and technology node, the same verified RTL ships with toolchain-specific constraints, integration scripts, and a full UVM verification suite, eliminating weeks of bringup effort.
Speak with a silicon engineer. We'll scope out your platform, lane width, and fab requirements — typically within one business day.