Production-proven 16 GT/s controller with x1–x16 lane configurations. Tailored for Xilinx, Altera, Microchip & Lattice FPGAs or custom ASIC on any fab and technology node of your choice.
The Xtremesilica PCIe Gen 4 IP core delivers industry-leading 16 GT/s per-lane throughput with a compact, cleanly partitioned RTL architecture optimised for both FPGA prototyping and high-volume ASIC production.
Whether you're targeting Zynq UltraScale+ for prototyping, Stratix 10 for a PCIe endpoint card, or a custom ASIC tape-out on your preferred fab and node, the same verified RTL ships with toolchain-specific constraint files, integration scripts, and a platform-tailored example design — eliminating weeks of bringup effort. Full Gen 1/2/3 backward compatibility ensures plug-and-play interoperability with all legacy hosts and devices.
Speak with a silicon engineer. We'll scope your lane count, endpoint/root port configuration, and fab requirements — typically within one business day.