Dual-generation LPDDR4 and LPDDR5 controller delivering up to 6400 MT/s with deep power-state management, bank-group scheduling, and Gear-2/4 mode — purpose-built for mobile SoCs, AI edge inference, automotive ADAS, and wearables where every milliwatt counts.
The LPDDR4/5 Controller IP delivers a unified controller supporting both LPDDR4/4X (up to 4267 MT/s) and LPDDR5/5X (up to 6400 MT/s) memory standards. Designed for power-sensitive SoCs, it implements the full JEDEC low-power feature set including Deep Sleep Mode (DSM), Partial Array Self-Refresh (PASR), and Fine Granularity Refresh.
LPDDR5 Gear-2 and Gear-4 modes decouple the PHY clock from the CA bus for efficient peak-rate operation. Bank-group interleaving and LPDDR5 sub-channel architecture deliver near-peak bandwidth with minimal latency for AI inference workloads in battery-constrained devices.