Full-featured I2C master and slave controller supporting all speed modes (Standard 100 kbps to High-Speed 3.4 Mbps), 7-bit and 10-bit addressing, multi-master arbitration, SMBus 3.0, and DMA — the most capable, lowest-footprint I2C peripheral for any SoC or FPGA design.
The I2C Controller IP implements the full NXP I2C specification v6 covering Standard Mode (100 kbps), Fast Mode (400 kbps), Fast Mode Plus (1 Mbps), and High-Speed Mode (3.4 Mbps). Both master and slave roles are supported simultaneously, and the multi-master arbitration engine handles bus contention transparently using standard clock stretching and SDA arbitration as defined by the I2C specification.
SMBus 3.0 extensions — SMBCLK/SMBALERT, Packet Error Checking (PEC) with CRC-8, and command protocol support — make the IP suitable for server management bus (PMBus, IPMI) and system power management applications. The tiny gate count (~400 LUTs on Xilinx UltraScale+) allows multiple instances to be deployed cost-effectively in multi-bus SoC designs.