Video Processing Production Ready FPGA Validated ASIC Ready

H.265 / HEVC
Codec IP Core

Real-time 4K@60fps and 8K@30fps encoder/decoder with up to 50% better compression than H.264. Tailored for any FPGA or custom ASIC on your preferred fab and technology node.

FPGA Validated

ITU-T H.265 Compliant

Custom ASIC Ready

ARM / RISC-V SoC

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Key SpecificationsRev 3.0

4K@60fps Real-time

8K@30fps Support

50%Better vs H.264

<50msLatency Mode

Platform Support

XilinxAlteraMicrochipCustom ASIC

Standards

ITU-T H.265 ✓ISO/IEC 23008-2Main 10 Profile

Product Overview

50% Better Compression.
Real-Time 4K & 8K.

The Xtremesilica H.265/HEVC Codec IP core delivers real-time encoding and decoding at 4K@60fps and 8K@30fps, achieving up to 50% better compression efficiency than H.264 at equivalent visual quality.

Supporting Main and Main 10 profiles up to Level 5.1, the codec integrates cleanly into ARM Cortex and RISC-V SoC subsystems via AXI4-Stream. Intelligent rate control (CBR/VBR/CQP), hardware-accelerated motion estimation, and ultra-low latency mode (<50ms) make it ideal for streaming, broadcast, surveillance, and automotive camera applications. Whether targeting Xilinx Zynq UltraScale+, Intel Arria 10, or a custom ASIC tape-out, the same verified RTL ships with platform-specific constraints and a full UVM verification suite.

4K@60Real-time encode

50%Compression gain

<50msLow-latency mode

Any FabAny node, your choice

Capabilities

Feature Highlights

Every layer engineered for compression efficiency, real-time throughput, and seamless SoC integration.

50% Superior Compression

Up to 50% better compression efficiency than H.264 at equivalent visual quality, enabling higher resolution streaming at significantly lower bitrates.

H.26530–50% bit reductionHEVC

4K / 8K Real-Time Support

Real-time encoding and decoding of 4K@60fps and 8K@30fps content with full HDR (High Dynamic Range) and wide colour gamut support.

4K@60fps8K@30fpsHDR

Multi-Stream Processing

Simultaneous encoding and decoding of multiple independent video streams with configurable quality settings, resolution, and frame rate per stream.

Multi-streamIndependent controlParallel

Adaptive Bit Rate Control

Intelligent rate control with CBR (Constant Bit Rate), VBR (Variable Bit Rate), and CQP (Constant Quality) modes with scene-adaptive encoding algorithms.

CBR / VBRCQPScene-adaptive

Ultra-Low Latency Mode

Dedicated low-latency encoding pipeline delivering <50ms end-to-end latency for real-time applications including video conferencing and live streaming.

<50ms latencyLive streamingConferencing

Error Resilience & Quality Metrics

Advanced error concealment, slice-based encoding for resilience, and objective quality metrics (PSNR, SSIM) for perceptual quality optimisation and monitoring.

Slice encodingPSNR / SSIMError concealment

Technical Data

Full Specifications

Complete parameter set for system architecture and integration planning.

Codec Standard

Standard

ITU-T H.265 / ISO/IEC 23008-2 HEVC

Profiles

Main, Main 10 (HDR)

Level

Up to Level 5.1

Chroma Format

4:2:0, 4:2:2, 4:4:4

Bit Depth

8-bit / 10-bit (HDR)

Resolution & Performance

Max Resolution

8K UHD (7680×4320)

4K Frame Rate

3840×2160 @ 60 fps

8K Frame Rate

7680×4320 @ 30 fps

Min Resolution

128×128 pixels

Latency Mode

<50 ms low-latency

Encoding Configuration

Rate Control

CBR / VBR / CQP

Compression Gain

30–50% vs H.264

GOP Structure

Configurable I/P/B frames

CTU Block Size

64×64 max CTU

Slice Encoding

Multi-slice for resilience

System Interface

Video Interface

AXI4-Stream (64/128/256-bit)

Config Interface

AXI4-Lite (32-bit)

Frame Buffer DMA

Scatter-gather DMA

Interrupts

MSI / MSI-X

ASIC Technology

Any fab — 180nm → 3nm

Supported Platforms

FPGA & Custom ASIC Targets

Every platform ships with pre-tested constraints, example designs, and integration scripts.

Xilinx (AMD)

Vivado / Vitis

Zynq UltraScale+ MPSoCVersal ACAPArtix UltraScale+

Vivado IP Integrator block design packaged
Zynq MPSoC PS–PL AXI video pipeline example
Versal AI engine integration reference
XDC timing constraints included

Altera (Intel)

Quartus Prime Pro

Arria 10Stratix 10Agilex F-Series

Platform Designer (Qsys) component ready
HPS AXI-Stream video bridge example
Frame buffer DDR4/DDR5 integration reference
SDC timing constraints included

Microchip

Libero SoC

PolarFire SoCPolarFire

SmartDesign component + PDC constraints
Mi-V RISC-V AXI4-Stream video example
Low-power video pipeline profile
Comprehensive TCL automation scripts

Lattice

Radiant / Diamond

CrossLink-NXCertusPro-NX

Radiant IP core package
LDC / PDC constraint files
Edge AI video pipeline example
Ultra-low power configuration profile

Use Cases

Target Applications

H.265/HEVC drives the world's most demanding video applications across every market segment.

Streaming Services

OTT video platforms delivering 4K/8K HDR content to global audiences with 30–50% bandwidth savings compared to H.264.

OTT / 4K HDRBandwidth savingAdaptive streaming

Professional Broadcasting

Broadcast equipment for terrestrial, satellite, and cable TV distribution requiring carrier-grade video compression and transmission.

Broadcast-gradeSatellite / CableTerrestrial

Video Conferencing

Real-time communication systems requiring sub-50ms encode latency for smooth interactive video calls and presentations.

Low latencyReal-timeInteractive

Surveillance Systems

IP cameras and NVR/DVR systems storing continuous multi-channel high-resolution footage with minimal storage overhead.

NVR / DVRMulti-channelStorage efficient

Automotive Cameras

ADAS and autonomous vehicle camera systems processing multiple high-resolution streams for driver assistance and event recording.

ADASAutonomousMulti-camera

Mobile Devices

Smartphones and tablets recording 4K video content with power-efficient hardware acceleration for extended battery life.

4K recordingPower efficientMobile SoC

What You Receive

Deliverables Package

Everything needed to move from licence to tape-out in the shortest possible time.

FPGA Implementation

Xilinx Vivado project + IP Integrator BD
Altera Quartus + Platform Designer component
Microchip Libero SoC SmartDesign component
Platform-specific XDC / SDC / PDC constraints
AXI4-Stream video pipeline reference design

Custom ASIC Implementation

Synthesisable RTL (SystemVerilog)
SDC timing constraints for foundry signoff
Synopsys / Cadence synthesis scripts
GDS layout (optional backend service)
ARM / RISC-V SoC integration reference

Verification Suite

UVM testbench — 100% functional coverage
H.265/HEVC protocol compliance tests
Directed + constrained-random regression
Interoperability test report

Documentation

Architecture & micro-architecture spec
Register map & programming guide
FPGA integration quick-start guide
Linux / RTOS driver source & guide

H.265 / HEVCCodec IP Core

50% Better Compression.Real-Time 4K & 8K.