High-performance multi-channel scatter-gather DMA engine with AXI4/AHB master interfaces, 32 independent channels, 256-bit data bus, descriptor chaining, and hardware flow control — the essential data-mover for high-throughput SoC and FPGA designs.
The DMA Engine IP is a versatile, silicon-proven data mover supporting memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers across up to 32 independent channels. Each channel is independently configurable with its own priority, burst length, and flow-control source, enabling deterministic data movement across complex SoC interconnects.
Scatter-Gather (SG-DMA) mode with linked-list descriptor chaining allows long, fragmented transfers to be submitted as a single operation, minimising CPU involvement. The 64-bit address master supports systems beyond 4 GB, and the configurable 32/64/128/256-bit AXI4 data bus width lets designers trade area for throughput on a per-integration basis.