Ethernet ControllerProduction Ready

400G
Ethernet

400 Gbps Ethernet MAC/PCS with IEEE 802.3bs compliance, RS-FEC, 8×50G lane breakout, and PFC-based lossless operation — designed for hyperscale switching, AI fabric, and cloud infrastructure.

IEEE 802.3bs RS-FEC 100% Wire Speed ASIC Ready

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Key Specifications

400 Gbps

Line Rate

8×50G

Lane Config

<500 ns

Latency

RS-FEC

Error Correction

Platform Support

XilinxAlteraMicrochipCustom ASIC

Standards

IEEE 802.3bsPFCDCQCN

Overview

400 Gbps for the Hyperscale Era

400 Gbps

Line Rate

8×50G

Lane Config

<500 ns

Cut-Through Latency

RS-FEC

544,514

The 400G Ethernet IP core delivers a complete IEEE 802.3bs MAC/PCS implementation with 8×50G PAM4 lane aggregation, RS-FEC (544,514) for reliable operation over DAC and optical media, and Priority Flow Control for lossless operation in RoCEv2 and AI training fabrics.

Built on the same proven architecture as our 100G core, the 400G IP supports flexible port segmentation (1×400G, 2×200G, 4×100G), enabling versatile switch ASIC designs for hyperscale and cloud deployments.

Features

Enterprise-Grade 400G Features

8×50G PAM4 Lanes

Eight 50 Gbps PAM4 lanes with independent lane training, skew compensation, and AM/marker lock for robust 400G operation over optical fiber and DAC.

RS-FEC (544,514)

Reed-Solomon Forward Error Correction per IEEE 802.3bs, enabling BER < 10⁻¹⁵ over PAM4 links with raw BER of 10⁻⁶, expanding reach without retries.

PFC Lossless Ethernet

8-class Priority Flow Control (IEEE 802.1Qbb) for lossless RoCEv2 transport in AI training and storage networks — prevents head-of-line blocking.

Flexible Port Modes

Runtime-reconfigurable port segmentation: 1×400G, 2×200G, 4×100G, or 8×50G — all from a single RTL instance on your switch ASIC.

AXI4-Stream Host Interface

Standard AXI4-Stream data interface up to 512-bit wide at 400G line rate, compatible with all major NPU and switching fabric IPs.

DCQCN Congestion Control

Data Center Quantized Congestion Notification (DCQCN) for ECN-based end-to-end congestion control in lossless Ethernet fabrics.

Specifications

Technical Specifications

MAC / PHY

StandardIEEE 802.3bs-2017

Line Rate400 Gbps

Lane Config8×50G PAM4

Encoding64b/66b per lane

FECRS-FEC (544,514)

Frame Size64 B – 16 KB (jumbo)

Quality of Service

PFC8 traffic classes (802.1Qbb)

QoS Classes8 priority queues

VLAN802.1Q double-tag

CongestionDCQCN / ECN

Latency< 500 ns cut-through

Host Interface

Data InterfaceAXI4-Stream (512-bit)

ManagementAXI4-Lite (32-bit)

Statistics64-bit RMON counters

InterruptMSI / MSI-X

Implementation

RTL LanguageSystemVerilog

FPGA SupportVersal, Agilex 9

ASIC Nodes3 nm → 12 nm

VerificationUVM, 100% coverage

Applications

400G Deployment Scenarios

🌐

Hyperscale Switching

Datacenter spine-leaf fabric switches with 400G uplinks and wire-speed L2/L3 forwarding.

🤖

AI Training Fabric

RoCEv2 lossless GPU interconnect networks for distributed AI model training at scale.

☁️

Cloud Infrastructure

Virtual switch ASICs in public cloud servers providing 400G north-south and east-west traffic.

💾

Storage Networking

NVMe-oF and RDMA storage fabrics demanding lossless 400G connectivity with PFC per traffic class.

📡

5G Core Networking

N4/N6 interfaces and UPF data plane processing at 400G for dense 5G standalone core deployments.

🔌

SmartNIC / DPU

400G DPU data plane with integrated MAC/PCS for server-side network offload and security.

🏢

Enterprise Core

Campus and enterprise core routers with 400G WAN interfaces and high-availability configurations.

🔬

HPC Interconnect

Ethernet-based HPC cluster interconnects leveraging RoCEv2 over lossless 400G fabric.

Deliverables

Everything You Need to Integrate

FPGA Implementation

Versal / Agilex 9 reference designVivado / Quartus project filesPlatform-specific constraints400G loopback test design

Custom ASIC

Synthesizable RTL (SystemVerilog)Synopsys / Cadence flow scriptsPHY wrapper for target nodeSDC timing constraints

Verification Suite

UVM testbench, 100% coverageIEEE 802.3bs compliance testsPFC / DCQCN stress testsMulti-port interop report

Documentation

Architecture specificationRegister map & driver guideLinux driver sourceP4/DPDK integration notes